IEEE

A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer

Abstract: A high-speed 2b-1b/cycle two-step successive-approximation-register analog-to-digital converter (ADC) exploiting the passive residue transfer technique is reported. The removal of the ...
IEEE

An 8-Bit 4-GS/s Single-Channel Two-Step ADC Featuring Non-Symmetrical Pipeline Timing and ...

Abstract: This article presents a single-channel 4-GS/s 8-bit hybrid-domain analog-to-digital converter (ADC) implemented in a 28-nm CMOS process. The proposed 8-bit ADC combines a 3-bit ...